Semiconductor integrated circuit device

ABSTRACT

A semiconductor integrated circuit device may include a first internal circuit operating at a first voltage higher than a power supply voltage of the device, and a second internal circuit operating at a second voltage lower than the first voltage. An interface circuit may be provided to restrict a voltage transferred from the first internal circuit to the second internal circuit. The first internal circuit may include a metal oxide semiconductor (MOS) transistor having a relatively thick gate insulation layer, and the second internal circuit may have a MOS transistor having a relatively thin gate insulation layer. The interface circuit, by restricting voltage, may reduce an electric field applied to the gate insulation layer of the second MOS transistor in an effort to prevent a reduction in turn-on speed of the second MOS transistor.

PRIORITY STATEMENT

[0001] This application claims the priority of Korean Patent ApplicationNo. 2003-8200, filed on Feb. 10, 2003 in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein in itsentirely by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor integratedcircuit device using a power supply voltage and other operationvoltages.

[0004] 2. Description of Related Art

[0005] Electronic apparatuses such as a personal digital assistant(PDA), a notebook computer or a mobile phone operate with a powersupplied from a battery. Users desire to use these electronicapparatuses for a longer time without recharge, which can be achieved bylowering operation current or operation voltage. In addition,state-of-the-art electronic apparatuses require higher operation speed.These state-of-the-art electronic apparatuses employ semiconductorintegrated current devices that include transistors such asmetal-oxide-semiconductor (MOS) transistors. In order to achieve higherspeed, it is desirable for a gate insulation layer of a MOS transistorto be formed so as to be of a relatively thin layer.

[0006] Additionally, an electronic apparatus operating with a loweroperation voltage includes a number of semiconductor integrated circuitdevices. The semiconductor integrated circuit device typically receivesan external power supply voltage, may have an internal power supplyvoltage, and may uses a voltage higher than the external or internalpower supply voltage. A relatively thick gate insulation layer is usedin a MOS transistor operating with a high voltage, so as to enhance awithstanding voltage relative to the high voltage. On the other hand, arelatively thin insulation layer is used in a MOS transistor operatingat a voltage other than (such as less than) the high voltage. Such aninsulation system is referred to as a “dual insulation system”.

[0007] In the case where a relatively thick gate insulation layer isemployed, it is possible to prevent the gate insulation layer from beingbroken due to a gate-drain voltage difference of a MOS transistor. Thethicker the gate insulation layer is, the higher a threshold voltage ofthe MOS transistor. When the threshold voltage of the MOS transistorrises, turn-on speed of the MOS transistor may be lowered. This maycause a reduction in system operation speed.

SUMMARY OF THE INVENTION

[0008] Exemplary embodiments of the present invention are directed to asemiconductor integrated circuit device. In an exemplary embodiment, thedevice may include a first internal circuit operating at a first voltagehigher than a power supply voltage of the device, and a second internalcircuit operating at a second voltage lower than the first voltage. Aninterface circuit may be provided to restrict a voltage transferred fromthe first internal circuit to the second internal circuit. The firstinternal circuit may include a metal oxide semiconductor (MOS)transistor having a relatively thick gate insulation layer, and thesecond internal circuit may include a MOS transistor having a relativelythin gate insulation layer. The interface circuit, by restrictingvoltage, may reduce an electric field applied to the gate insulationlayer of the second MOS transistor in an effort to prevent a reductionin turn-on speed of the second MOS transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a circuit diagram of a semiconductor integrated circuitdevice according to an exemplary embodiment of the present invention.

[0010]FIG. 2 is a diagram for explaining a difference between voltagesapplied to a gate insulation layer in a MOS transistor shown in FIG. 1.

[0011]FIG. 3 is a circuit diagram of a semiconductor integrated circuitdevice according to another exemplary embodiment of the presentinvention.

[0012]FIG. 4 is a circuit diagram of a semiconductor integrated circuitdevice according to another exemplary embodiment of the presentinvention.

[0013]FIG. 5 is a block diagram of a semiconductor memory deviceemploying the semiconductor integrated circuit device according to anexemplary embodiment of the present invention.

[0014]FIG. 6 is a circuit diagram showing a portion of a level shiftblock shown in FIG. 5.

[0015]FIG. 7 is a circuit diagram showing a portion of a row decoder anddriving block shown in FIG. 5.

[0016]FIG. 8 is a timing diagram for explaining a read operation of thesemiconductor memory device according to an exemplary embodiment of thepresent invention.

[0017]FIG. 9 is a block diagram of a semiconductor memory deviceaccording to another exemplary embodiment of the present invention.

[0018]FIG. 10 is a circuit diagram showing a portion of a row decoderand driving block shown in FIG. 9.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

[0019]FIG. 1 is a circuit diagram of a semiconductor integrated circuitdevice according to an exemplary embodiment of the present invention. Asemiconductor integrated circuit 10 outputs an output signal OUT inresponse to input signals IN1 and IN2. Semiconductor integrated circuit10 may include a first internal circuit 12, second internal circuit 14and interface circuit 16. The first internal circuit 12 may operate at ahigher voltage VPP than an internal power supply voltage IVC (or than anexternal power supply voltage EVC), while the second internal circuit 14and the interface circuit 16 may operate at the internal power supplyvoltage IVC (or the external power supply voltage EVC). The internalpower supply voltage IVC may equal the external power supply voltageEVC. Alternatively, the internal power supply voltage IVC may be lessthan the external power supply voltage EVC. The interface circuit 16 maylimit a voltage that is applied from the first internal circuit 12 tothe second internal circuit 14, or a voltage applied from an outputterminal OUT to the second internal circuit 14. The interface circuit 16may therefore act as a voltage-limiting means in the device 10.

[0020] The first internal circuit 12 may include a PMOS transistor MP1having a relatively thick gate insulation layer, so as to have asufficient withstand voltage relative to a high voltage VPP. The PMOStransistor MP1 is coupled so as to enable its gate to receive an inputsignal IN1, has a source coupled to a power terminal receiving the highvoltage VPP, and has a drain coupled to the output terminal OUT.

[0021] The interface circuit 16 may include an NMOS transistor MN1having a relatively thin gate insulation layer, so as to have awithstand voltage relative to the IVC/EVC voltage. The NMOS transistorMN1 has a gate coupled to the IVC/EVC voltage, a drain coupled to theoutput terminal OUT, and a source coupled to the second internal circuit14.

[0022] The second internal circuit 14 may include an NMOS transistor MN2having a relatively thin gate insulation layer, so as to have awithstand voltage relative to the IVC/EVC voltage. The NMOS transistorMN2 is coupled so its gate can receive an input signal IN2, has a draincoupled to the source of the NMOS transistor MN1, and has a sourcecoupled to a ground voltage VSS.

[0023] The input signal IN1 may selectively have a ground voltage VSSand a high voltage VPP. The input signal IN2 may selectively have aground voltage VSS and an internal power supply voltage IVC (or externalpower supply voltage EVC).

[0024] The NMOS transistor MN1 of the interface circuit 16 prevents ahigh voltage supplied through a PMOS transistor MP1 from being directlyapplied to the drain of the NMOS transistor MN2. That is, since avoltage of the output terminal OUT is transferred through the NMOStransistor MN1 (whose gate is coupled to the IVC/EVC voltage), a voltageof IVC/EVC-Vtn1 instead of the high voltage VPP is applied to the drainof the NMOS transistor MN2, where Vtn1 denotes a threshold voltage of anNMOS transistor having a relatively thin gate insulation layer. Sincethe IVC/EVC is always applied to the gate of the NMOS transistor MN1, agate-drain voltage difference of the NMOS transistor MN1 is VPP-IVC/EVC.Therefore, although the NMOS transistor MN1 has the relatively thin gateinsulation layer, a gate insulation layer of the NMOS transistor MN1 isnot broken by the high voltage VPP.

[0025]FIG. 2 is a diagram for explaining a difference between voltagesapplied to a gate insulation layer in a MOS transistor shown in FIG. 1.If the NMOS transistor MN1 is not used, a gate-drain voltage differenceVgd1 of the NMOS transistor MN2 is the maximum VPP voltage, as shown inFIG. 2. This means that, in a case where an NMOS transistor MN2 with arelatively thin gate insulation layer is used, the gate insulation layerof the NMOS transistor MN2 is broken. Thus, it is desired that the NMOStransistor MN2 have a relatively thick gate insulation layer. In thiscase, the input signal IN2 of the NMOS transistor MN2 has a high voltageVPP during an active state. If not, the turn-on speed of the NMOStransistor MN2 may be lowered.

[0026] On the other hand, when the NMOS transistor MN1 is used, agate-drain voltage difference Vgd2 of the NMOS transistor MN2 is themaximum IVC voltage (when IVC is lower than EVC), as shown in FIG. 2.When the IVC is equivalent to the EVC, the gate-drain voltage differenceVgd2 of the NMOS MN2 is IVC-Vtnh. In other words, an electric fieldapplied to the gate insulation layer of the NMOS transistor MN2 may bealleviated. Therefore, the NMOS transistor MN1 may be used as aninterface (or for attenuating an electric field) and may be arrangedbetween the internal circuits 12 and 14. NMOS transistor NM1 preventsthe gate insulation layer of the NMOS transistor MN2 from being brokenby applying a high voltage to the drain of NMOS transistor MN2, as wellas to prevent any lowering of the turn-on speed of the NMOS transistorMN2.

[0027]FIG. 3 is a circuit diagram of a semiconductor integrated circuitdevice according to another exemplary embodiment of the presentinvention. In FIG. 3, a semiconductor integrated circuit device 20includes circuit 26 that limits a voltage applied from a first internalcircuit 22 to a second internal circuit 24, and which acts as avoltage-limiting means (or a field-alleviating means). The firstinternal circuit 22 may include PMOS transistors MP2 and MP3, at leastone or both having a relatively thick gate insulation layer, so as tohave a sufficient withstand voltage relative to a high voltage VPP. ThePMOS transistor MP2 has a source coupled to the high voltage VPP, adrain coupled to an internal node ND1, and a gate coupled to receive aninput signal IN1. The input signal IN1 may selectively have a highvoltage VPP and a ground voltage VSS. The PMOS transistor MP3 has asource coupled to the high voltage VPP, a drain coupled to the internalnode ND1, and a gate coupled to an output terminal OUT.

[0028] The interface circuit 26 may include an NMOS transistor MN3 witha relatively thin gate insulation layer, so as to have a sufficientwithstand voltage relative to an internal power supply voltage IVC orrelative to an external power supply voltage EVC. The NMOS transistorMN3 has a gate coupled to an internal power supply voltage IVC or anexternal power supply voltage EVC, a drain coupled to an internal nodeND1, and a source coupled to the second internal circuit 24.

[0029] The second internal circuit 24 may include NMOS transistors MN4,MN5, MN6 and MN7, each with a relatively thin gate insulation layer soas to have a sufficient withstand voltage relative to an internal powersupply voltage IVC or relative to an external power supply voltage EVC.The NMOS transistors MN4-MN7 may be serially coupled between theinterface circuit 26, i.e., between the source of the NMOS transistorMN3 and the ground voltage VSS, and may be controlled by correspondinginput signals IN2, IN3, IN4 and IN5. Each of the input signals IN2-IN5may have an internal power supply voltage IVC or an external powersupply voltage EVC in an active state, and may have a ground voltage VSSin an inactive state.

[0030] An inverter INV may be coupled between an internal node ND1 andan output terminal OUT. The INV may include PMOS transistor MP4 and NMOStransistor MN8. Each of the transistors MP4 and MN8 may have arelatively thick gate insulation layer so as to have a sufficientwithstand voltage relative to a high voltage VPP. The PMOS and NMOS MP4and MN8 may be serially coupled between a high voltage VPP and a groundvoltage VSS. Gates of the PMOS and NMOS transistors MP4 and MN8 may becommonly connected to an internal node ND1, as shown in FIG. 3.

[0031] Referring again to FIG. 3, in operation, when an input signal IN1is at a low level of ground voltage VSS and at least one of inputsignals IN2-IN5 is at a low level of a ground voltage VSS, internal nodeND1 may be precharged to high voltage VPP through PMOS transistor MP2.In this case, the output signal OUT becomes a low level of the groundvoltage VSS, so that PMOS transistor MP2 is also turned on. Since thegate of NMOS transistor MN4 (coupled to an internal power supply voltageIVC or an external power supply voltage EVC) is always in a turn-onstate, a voltage of IVC-Vtn1 is applied to the drain of NMOS transistorMN4 through NMOS transistor MN3. That is, a voltage applied to the drainof the NMOS transistor MN4 is restricted by NMOS transistor MN3 of theinterface circuit 26. Accordingly, although NMOS transistor MN4 has arelatively thin gate insulation layer, the gate insulation layer of theNMOS transistor MN4 is not broken by the high voltage VPP, and a turn-onspeed of NMOS transistor NM4 does not need to be lowered. Similarly,since IVC/EVC is always applied to the gate of the NMOS transistor MN3,a gate-drain voltage difference of NMOS transistor MN3 is VPP-IVC/EVC.Although NMOS transistor MN3 has a relatively thin gate insulationlayer, the gate insulation layer of the NMOS transistor MN3 is notbroken by the high voltage VPP.

[0032] When an input signal IN1 has a high level a high voltage VPP andinput signals IN2-IN5 have a high level of IVC/EVC, voltage of theinternal node ND1 is discharged through interface circuit 26 and secondinternal circuit 24, i.e., NMOS transistors MN3-MN7. The output signalOUT has a high level through inverter INV1.

[0033]FIG. 4 is a circuit diagram of a semiconductor integrated circuitdevice according to another exemplary embodiment of the presentinvention. In FIG. 4, a semiconductor integrated circuit device 30includes a first internal circuit 32. The first internal circuit 32includes PMOS transistors MP5 and MP6 with a relatively thick gateinsulation layer, so as to have a sufficient withstand voltage relativeto the high voltage VPP. The PMOS transistor MP5 has a source coupled tothe high voltage VPP, a drain coupled to the internal node ND2, and agate coupled to an internal node ND3. The PMOS transistor MP6 has asource coupled to the high voltage VPP, a drain coupled to the internalnode ND3, and a gate coupled to the internal node ND2.

[0034] The semiconductor integrated circuit device 30 also includes asecond internal circuit 34. The second internal circuit 34 includes NMOStransistors MN11 and MN12 and an inverter INV2, and may operate with aninternal power supply voltage IVC or with an external power supplyvoltage EVC, for example. Each of the NMOS transistors MN11 and MN12 hasa relatively thin gate insulation layer, so as to have a sufficientwithstand voltage relative to an internal power supply voltage IVC, orrelative to an external power supply voltage EVC. The NMOS transistorMN11 has a drain coupled to an internal node ND4, a source coupled to aground voltage VSS, and a gate connected to receive an input signal IN.The NMOS transistor MN12 has a drain coupled to an internal node ND5, asource coupled to a ground voltage VSS, and a gate connected to receivean inverted input signal INB through an inverter INV2. The inverter INV2operates with an internal power supply voltage IVC or with an externalpower supply voltage EVC. Inverter INV2 may include PMOS and NMOStransistors (not shown) with a relatively thin gate insulation layer.

[0035] The semiconductor integrated circuit device 30 also includes aninterface circuit 36. The interface circuit 36 reduces an electric fieldapplied to a gate insulation layer of NMOS transistors MN11 and MN12,and restricts a voltage applied from the internal node ND2 or ND3 to thesecond internal circuit 34. The interface circuit 36 may include NMOStransistors MN9 and MN10, each with a relatively thin gate insulationlayer so as to have a sufficient withstand voltage relative to aninternal power supply voltage IVC, or relative to an external powersupply voltage EVC. The NMOS transistor MN9 may be coupled betweeninternal nodes ND2 and ND4, and the NMOS transistor MN10 is coupledbetween internal nodes ND3 and ND5. Gates of NMOS transistors MN9 andMN10 may be commonly coupled to an internal power supply voltage IVC oran external power supply voltage EVC, for example.

[0036] In operation, when an input signal IN is at a low level, NMOStransistor MN11 is turned off and MOS transistor MN12 is turned on.Since the ND3 node goes to a low level through NMOS transistors MN10 andMN12, PMOS transistor MP5 is turned on and an output signal goes to ahigh level of high voltage VPP. When the input signal is at a highlevel, the NMOS transistor MN13 is turned off and the NMOS transistorMN11 is turned on. Since the ND2 node goes to a low level through NMOStransistors MN9 and MN11, the PMOS transistor MP6 is turned on and anoutput signal OUT goes to a low level of ground voltage VSS.

[0037] Since each of NMOS transistors MN9 and MN10 has a gate coupled toan internal power supply voltage IVC and an external voltage is alwaysturned on, a voltage IVC/EVC-Vtn1 is applied to NMOS transistors MN11 orMN12, through NMOS transistor MN9 or MN10. In other words, a voltageapplied to the drain of either NMOS transistor MN11 or MN12 isrestricted by NMOS transistor MN9 or MN10 of the interface circuit 36.Accordingly, although NMOS transistors MN11 and MN12 each have arelatively thin gate insulation layer, the gate insulation layers ofNMOS transistors MN11 and MN12 are not broken by the high voltage VPP.Further, since each of the NMOS transistors MN11 and MN12 has arelatively thin gate insulation layer, the turn-on speed of the NMOStransistors MN11 and MN12 is not reduced. Likewise, since IVC/EVC isalways applied to the gates of the NMOS transistors MN9 and MN10, agate-drain voltage difference of the respective NMOS transistors MN9 andMN10 is VPP-IVC/EVC. Although the NMOS transistor MN9 and MN10 haverelatively thin gate insulation layers, the gate insulation layers ofthe NMOS transistors MN9 and MN10 are not broken by the high voltageVPP.

[0038]FIG. 5 is a block diagram of a semiconductor memory deviceemploying the semiconductor integrated circuit device according to anexemplary embodiment of the present invention. Referring to FIG. 5,semiconductor memory device 100 may include a memory cell array 110having a plurality of memory blocks MB0, MB1, . . . , and MBy. Each ofthe memory blocks MB0, MB1, . . . , and MBy may include memory cellsdisposed in a matrix of rows (or word lines) or columns (bit lines). Arow predecoder 120 generates decoding signals DRAi[0:m], DRAj[0:n], andDRAk[0:x] and block selecting signals BLK[0:y]. The block selectingsignals BLK[0:y] correspond to the memory blocks MB0-MBy. The decodingsignals DRAi[0:m], DRAj[0:n], and DRAk[0:x] may be used to select one ofthe word lines of a selected memory block.

[0039] The semiconductor memory device 100 may include a plurality oflevel shift blocks LSB0, LSB1, . . . , and LSBy, each corresponding tomemory blocks MB0-MBy. Each of the level shift blocks LSB0-LSBy inputs acorresponding a block selecting signal BLK[O:Y] and a decoding signalDRAk[0:x]. For example, the level shift block LSB0 inputs the blockselecting signal BLK0 and the decoding signals DRAk[0:x], the levelshift block LSB1 inputs the block selecting signal BLK1 and the decodingsignals DRAk[0:x], and the level shift block LSBy inputs the blockselecting signal BLKy and the decoding signals DRAk[0:x].

[0040] During an active state, input signals of the level shift blocksLSB0-LSBy each may be at an internal power supply voltage IVC, or at anexternal power supply voltage EVC. The level shift blocks LSB0-LSByoutput decoding signals (including block selecting information) inresponse to the input signals. For example, the level shift block LSB1outputs decoding signals DRAlk[0:x] in response to input signals, andthe level shift block LSBy outputs decoding signals DRAyk[0:x] inresponse to input signals.

[0041] The semiconductor memory device 100 further includes row decoderand driver blocks 130_0, 130_1, . . . , and 130_y, each correspondingthe memory blocks MB0, MB1, . . . , and MBy. The row decoder and driverblocks 130_0, 130_1, . . . , and 130_y operate with a high voltage VPP.Each of the row decoder and driver circuits 131 drives a correspondingword line in response to a part of the decoding signals DRAi[0:m] andDRAj[0:n] from the row predecoder 120 and a part of the decoding signals(e.g., DRAOk[0:x] from a corresponding level shift block (e.g., LSB0).

[0042] The level shift blocks and the row decoder and driving blocksaccording to the exemplary embodiments of the present invention may beimplemented using a dual circuit device of a dual insulation system, asdescribed in any of FIG. 1, FIG. 3 and FIG. 4, for example. As shown inFIG. 5, outputs signals of the respective level shift blocks may only beinput to corresponding memory blocks, in an effort to reduce powerconsumption.

[0043]FIG. 6 is a circuit diagram showing a part of the level shiftblock of in FIG. 5. In FIG. 6, a level shift circuit LS is one of thelevel shift circuits of the level shift block that corresponds todecoding signals DRAk0-DRAkx. The other level shift circuits may havethe same construction as the level shift circuit LS shown in FIG. 6. Thelevel shift circuit LS outputs a decoding signal DRA0 k 0, in responseto a decoding signal DRAk0 and a block selecting signal BLK0. Thedecoding signal DRAk0 and the block selecting signal BLK0 may have aninternal power supply voltage IVC or an external power supply voltageEVC, for example during the active state. The decoding signal DRA0 k 0may have a high voltage VPP during the active state. The level shiftcircuit LS may include two PMOS transistors MP20 and MP21, four NMOStransistors MN20, MN21, MN22, and MN23, an inverter INV20, and a NANDG20, for example.

[0044] PMOS transistors MP20 and MP21 each may have a relatively thickgate insulation layer, so as to have a sufficient withstand voltagerelative to a high voltage. Each of NMOS transistors MN20-MN23 may havea relatively thin gate insulation layer, so as to have a sufficientwithstand voltage relative to one of an internal power supply voltageIVC and an external power supply voltage EVC, for example. Although notshown in FIG. 6, NMOS transistors constituting the NAND gate G20 and theinverter INV20 may also have a relatively thin gate insulation layer, soas to have a sufficient withstand voltage relative to an internal powersupply voltage IVC or an external power supply voltage EVC.

[0045] PMOS transistor MP20 has a gate coupled to node ND21, a sourcecoupled to a high voltage VPP, and a drain coupled to node ND20 (outputterminal DRA0 k 0). PMOS transistor MP21 has a gate coupled to nodeND20, a source coupled to a high voltage VPP, and a drain coupled tonode ND21. The NMOS transistors MN20 and MN22 may be serially coupledbetween node ND20 and a ground voltage VSS. The NMOS transistors MN21and MN23 may be serially coupled between ND21 and a ground voltage VSS.Gates of the MOS transistors MN20 and 21 may be connected to internalpower supply voltage IVC and to external power supply voltage EVC. NMOStransistor MN22 may be controlled by a clock signal NOUT of an NAND gateG20 operating in response to the decoding signal DRAk0 and the blockselecting signal BLK0. Inverter INV20 inverts an output signal of theNAND gate G20. NMOS transistor MN23 is controlled by an output signal ofthe inverter INV20.

[0046] In operation, when at least one of the decoding signal DRA0 k andthe block selecting signal BLK0 is at a low level, NMOS transistor MN22is turned on and NMOS transistor MN23 is turned off. Accordingly, thenode ND20 has a low level through NMOS transistors MN20 and MN22. AsPMOS transistor MP21 is turned on, node ND21 is of a high voltage VPPand PMOS transistor MP20 is turned off. Although the node ND21 is at thehigh voltage VPP, NMOS transistors MN21 and MN23 (each having relativelythin gate insulation layers) are not affected by the high voltage VPP.This is because a gate-drain voltage difference of the NMOS transistorMN21 (where its gate is coupled to IVC/EVC) is VPP-IVC/EVC, and thegate-drain voltage difference of NMOS transistor MN23 is IVC/EVC-Vtn1.

[0047] When the decoding signal DRA0 k and the block selecting signalBLK0 are at a high level, NMOS transistor MN22 is turned off and NMOStransistor MN23 is turned on. Accordingly, node ND21 is at a low levelthrough NMOS transistors MN21 and MN23. As PMOS transistor MP20 isturned on, node ND20 is at high voltage VPP, and PMOS transistor MP21 isturned off. An output signal DRA0 k 0 (including block selectinginformation) has a high voltage VPP. Although node ND20 is at highvoltage VPP, NMOS transistors MN20 and MN22 (each having a relativelythin gate insulation layer) are not affected by the high voltage VPP.This is because a gate-drain voltage difference of NMOS transistor MN20(having its gate coupled to IVC/EVC) is VPP-IVC/EVC, and a gate-drainvoltage difference of NMOS transistor MN22 is IVC/EVC-Vtn1.

[0048] In this exemplary embodiment, PMOS transistors MP20 and MP21 mayconstitute a ‘first internal circuit’ operating with a high voltage VPP.The NAND gate G20, inverter INV20, and NMOS transistors MN22 and MN23may constitute a ‘second internal circuit’ operating with an internalpower supply voltage IVC and an external power supply voltage EVC. NMOStransistors MN20 and MN21 may constitute means for restricting a voltagetransmitted from the first internal circuit to the second internalcircuit, for example.

[0049]FIG. 7 is a circuit diagram showing a part of the row decoder anddriver block of FIG. 5. A row decoder and driver circuit 131 of FIG. 7may be coupled to one of a plurality of word lines, each word linecorresponding to a row decoder and driver block 130_0˜130_y. Each rowdecoder and driver circuit may have the same construction as the rowdecoder and driver circuit shown in FIG. 7. The circuit 131 drives acorresponding word line in response to decoding signals (e.g., DRA0 k 0,DRAi0, and DRAj0). A decoding signal DRA0 k 0 is input from acorresponding level shift block at a high level of a high voltage duringan active state of the device employing circuit 131. The decodingsignals DRAi0 and DRAj0 are input from the row predecoder 120 of FIG. 5,and may have either an internal power supply voltage IVC or an externalpower supply voltage EVC during the active state, for example.

[0050] Referring to FIG. 7, the row decoder and driver circuit 131 mayinclude PMOS transistors MP22, MP23 and MP24 and NMOS transistors MN24,MN25, MN26 and MN27. PMOS transistor MP22 has a gate connected toreceive a control signal P_0, a source coupled to a high voltage VPP,and a drain coupled to an internal node ND22. The NMOS transistorsMN24-MN26 may be serially coupled between the internal node ND24 and aground voltage VSS, and are controlled by corresponding decoding signalsDRA0 k 0, DRAi0, and DRAj0. PMOS transistor MP23 has a gate coupled toan output terminal ND24, a source coupled to a high voltage VPP, and adrain coupled to an internal node ND23. PMOS transistor MP24 and NMOStransistor MN27 may constitute an inverter, and are coupled between theinternal node ND22 and the output terminal ND24 (i.e., a word line WL).

[0051] In operation, when the control signal P_0 is at a low level andat least one of the decoding signals DRA0 k 0, DRAi0, and DRAj0 is at alow level, a current path between the internal node ND22 and the groundvoltage VSS is cut off, and a current path is formed between theinternal node ND22 and the high voltage VPP. Since the PMOS transistorMP22 is turned on, the node ND22 has a high level of a high voltage VPP.Therefore, the wordline WL has a low level. Since the NMOS transistorMN24 has a relatively thick gate insulation layer even though thedecoding signal DRA0 k 0 has a low level, the gate insulation layer ofthe NMOS transistor MN24 is not affected by the high voltage VPP of thenode ND22. Although the decoding signal DRA0 k 0 has a high level of thehigh voltage VPP and the decoding signal DRA10 has a low level of theground voltage VSS, the gate insulation layer of the NMOS transistorMN25 is not affected by the high voltage VPP. This is because theinternal node ND23 has a voltage of VPP-Vtnh. The “Vtnh” means athreshold voltage of the NMOS transistor having a relatively thick gateinsulation layer and is, for example, 2Vtn1.

[0052] When the control signal P_0 has a high level of a high voltageVPP and all decoding signals DRA0 k 0, DRA10, and DRAj0 are at a highlevel, a current path between the high voltage VPP and the internal nodeND22 while a current path is formed between the internal node ND22 andthe ground voltage VSS. Accordingly, the word line WL is driven with thehigh voltage VPP through PMOS transistor MP24. Since the high voltageVPP of node ND22 is transmitted through NMOS transistor MN24 (serving asan interface or voltage restricting means), a gate insulation layer ofthe NMOS transistor MN27 is not affected by the high voltage VPP.

[0053]FIG. 8 is a timing diagram for explaining a read operation of asemiconductor memory device according to an exemplary embodiment of thepresent invention. In operation, when a control signal P_0 and decodingsignals DRAykx, DRAim, and DRAjn are at a high level, the PMOStransistor MP22 shown in FIG. 7 is turned on and the NMOS transistorsMN24-MN26 shown in FIG. 7 are turned off. Accordingly, word lines go toa low level.

[0054] As shown in FIG. 8, as the control signal P_0 goes to a highlevel, the PMOS transistor MP23 shown in FIG. 7 is turned off. Blockselecting signals BLK[0:y] and decoding signals DRAk[0:x] are input tocorresponding level shift blocks LSB0-LSBj. A level shift blockcorresponding to a selected memory block shifts a voltage level ofdecoding signals having a high level of IVC/EVC to a high voltage VPP.As shown in FIG. 8, high-level decoding signals output from the levelshift block have a high voltage VPP, instead of an internal power supplyvoltage IVC or an external power supply voltage EVC, throughcorresponding level shift circuits (see FIG. 6). Thereafter, one of therow decoder and driver circuits in a selected memory block operates aword line WL with a high voltage VPP in response to the input signalsDRAykx, DRAim, and DRAjn.

[0055] As previously stated, a MOS transistor (such as NMOS transistorMN24 of FIG. 7) having a relatively thick gate insulation layer may beused for preventing a gate insulation layer from being broken by a highvoltage in an integrated circuit employing a dual insulation system. Inthe case where a voltage applied to the gate of the NMOS transistor MN24is an internal power supply voltage IVC or an external power supplyvoltage EVC, the high voltage VPP of node ND22 shown in FIG. 7 may bedischarged along a dotted line of FIG. 8. This is because it isdifficult to sufficiently turn on the NMOS transistor having therelatively thick gate insulation layer by using IVC/EVC. As a result,the activation speed of the word line WL is lowered.

[0056] In case of the semiconductor memory device according to theinvention, however, the gate voltage of the NMOS transistor MN24 is setto a high voltage to turn on the NMOS transistor MN24 having therelatively thick gate insulation layer in a sufficiently high speed.Thus, a discharge speed of the ND22 voltage of the row decoder anddriver circuit 131 makes higher by tD, as shown in FIG. 8. As a result,the activation speed of the word line WL becomes higher by tD.

[0057]FIG. 9 is a block diagram of a semiconductor memory deviceaccording to another exemplary embodiment of the present invention, andFIG. 10 is a circuit diagram showing a portion of a row decoder anddriving block of FIG. 9.

[0058] Unlike the row decoder and driver blocks shown in FIG. 5, rowdecoder and driver blocks 130′_0˜130′_y of FIG. 10 receive outputsignals directly from a row predecoder 120′ (the output signals do notgo through corresponding level shift blocks LSB0 . . . LSBy). The rowdecoder and driver blocks of FIG. 10 have a dual insulation system so asto operate with a high voltage VPP and an internal power supply voltageIVC or an external power supply voltage EVC.

[0059] Referring to FIG. 10, a given row decoder and driver block 131′may be coupled to any word line, drives the word line WL with a highvoltage VPP in response to decoding signals DRAim, DRAjn, DRAkx, andBLKy. Each of the decoding signals has an internal power supply voltageIVC or an external power supply voltage EVC during the active state. Thesemiconductor memory device shown in FIG. 9 adopts the interface asshown in FIG. 3, but does not employ the level shift blocks of FIG. 5,for example.

[0060] The row decoder and driver circuit 131′ may include PMOStransistor P25, MP26 and MP27 and the NMOS transistors MN28, MN29, MN30,MN31, MN32 and MN33. Each of the transistors MP25, MP26, MP27 and MN33may have a relatively thick gate insulation layer. Each of thetransistors MN28-MN32 may have a relatively thin gate insulation layer.PMOS transistors MP25 and MP26 may constitute a first internal circuitoperating with a high voltage VPP, and NMOS transistors MN29-MN32 mayconstitute a second internal circuit operating with an internal powersupply voltage IVC or an external power supply voltage EVC. The NMOStransistor MN28 may act as an interface circuit (or voltage restrictingmeans) for restricting a voltage applied from the first internal circuitto the second internal circuit. The row decoder and driver circuit ofFIG. 10 operates the same as the integrated circuit device of FIG. 3,thus operation will not be explained in further detail.

[0061] As described above, since the high voltage VPP of the node ND25is transmitted to the drain of the NMOS transistor MN29 through the NMOStransistor MN28, a gate-drain voltage difference of the NMOS transistorMN29 is IVC/EVC-Vtn1. Thus, although the NMOS transistor MN29 has arelatively thin gate insulation layer, the gate insulation layer of theNMOS transistor MN29 is not affected by the high voltage VPP. SinceIVC/EVC is always applied to the gate of the NMOS transistor MN28, agate-drain voltage difference of the NMOS transistor is VPP-IVC/EVC.Although the NMOS transistor MN28 has a relatively thin gate insulationlayer, the gate insulation layer of the NMOS transistor MN28 is notbroken by the high voltage VPP.

[0062] In accordance with the exemplary embodiments described above, anvoltage IVC/EVC may be applied to a MOS transistor constituting aninterface circuit or voltage restricting means. However, a gate voltageof this MOS transistor may be variously regulated so that a relativelythin gate insulation layer is not affected. To regulate the gatevoltage, for example, a voltage between an internal (or external) powersupply voltage and a high voltage or a voltage between an internal (orexternal) power supply voltage and a ground voltage may be used.

[0063] While the present invention has been set forth and described withrespect to the above exemplary embodiments, it will be appreciated thatother and different systems could readily be designed by those skilledin the art, without significantly departing from the spirit and scope ofthe exemplary embodiments of the present invention.

What is claimed is:
 1. A semiconductor integrated circuit device,comprising: a first internal circuit including a first metal-oxidesemiconductor (MOS) transistor operating at a first voltage higher thana power supply voltage of the device; a second internal circuitincluding a second MOS transistor operating at a second voltage lowerthan the first voltage; and restricting means for restricting a voltagetransmitted from the first internal circuit to the second internalcircuit.
 2. The device of claim 1, wherein the first MOS transistor hasa relatively thick gate insulation layer, the second MOS transistor hasa relatively thin gate insulation layer, and the voltage transmittedfrom the first internal circuit to the second internal voltage reducesan electric field applied to the gate insulation layer of the second MOStransistor.
 3. The device of claim 1, wherein the power supply voltageis an external power supply voltage for the device or an internal powersupply voltage of the device, and the second voltage is one of the powersupply voltage, a voltage lower than the power supply voltage, and avoltage between the power supply voltage and the first voltage.
 4. Thedevice of claim 1, wherein the restricting means includes a third MOStransistor having a relatively thin gate insulation layer and operatingat the second voltage, the voltage from the first internal voltage isapplied to the second internal circuit through the third MOS transistor,and the second MOS transistor is controlled by a row address signal in amemory device.
 5. The device of claim 4, further comprising: an invertercoupled to a connection node of the second and third MOS transistors,wherein the inverter drives a word line in the memory device.
 6. Thedevice of claim 5, wherein the inverter includes PMOS and NMOStransistors, each PMOS or NMOS transistor operating at a voltage higherthan the power supply voltage and having a relatively thick gateinsulation layer.
 7. The device of claim 1, wherein the restrictingmeans includes a third MOS transistor operating at the first voltage andhaving a relatively thick gate insulation layer, and the third MOStransistor is controlled by a row address signal in a memory device, therow address signal being at the first voltage when the memory device isin an active state.
 8. The device of claim 7, further comprising: aninverter coupled to a connection node of the second and third MOStransistors, wherein the inverter drives a word line in the memorydevice.
 9. The device of claim 8, wherein the inverter includes PMOS andNMOS, each PMOS or NMOS transistor operating at a voltage higher thanthe power supply voltage and having a relatively thick gate insulationlayer.
 10. A semiconductor integrated circuit device, comprising: apower terminal receiving a first high voltage that is higher than apower supply voltage of the device; a first transistor having a draincoupled to the power terminal, a source coupled to the first highvoltage, and a gate coupled to a first input signal; a second transistorhaving a drain coupled to the power terminal, a source, and a gatecoupled to a second low voltage that is lower than the first highvoltage; and a third transistor having a drain coupled to the source ofthe second transistor, a source coupled to a ground voltage, and a gatecoupled to a second input signal, wherein the first transistor has arelatively thick gate insulation layer, and the second and thirdtransistors each have a relatively thin gate insulation layer.
 11. Thedevice of claim 10, wherein the power supply voltage is an externalpower supply voltage for the device or an internal power supply voltageof the device, and the second low voltage is one of the power supplyvoltage, a voltage lower than the power supply voltage, and a voltagebetween the power supply voltage and the first high voltage.
 12. Thedevice of claim 10, wherein the first input signal is selectable as oneof a high level of the first high voltage and a low level of the groundvoltage.
 13. The device of claim 10, wherein the second input signal isselectable as one of a high level of the second low voltage and a lowlevel of the ground voltage.
 14. The device of claim 10, wherein thesecond input signal includes a row address signal from a memory device.15. The device of claim 14, further comprising: an inverter coupled to aconnection node of the second and third transistors, wherein theinverter drives a word line of the memory device.
 16. The device ofclaim 15, wherein the inverter includes PMOS and NMOS transistors, eachPMOS or NMOS transistor operating at a voltage higher than the powersupply voltage and having a relatively thick gate insulation layer. 17.The device of claim 10, further comprising: a fourth transistor coupledbetween the third transistor and the ground voltage, wherein the fourthtransistor has a relatively thin gate insulation layer.
 18. The deviceof claim 17, wherein the fourth transistor is controlled by a blockselecting signal from a memory device.
 19. A semiconductor integratedcircuit device, comprising: a power terminal receiving a first highvoltage higher than a power supply voltage of the device; a first MOStransistor coupled between the power terminal and a first internal node;a second MOS transistor coupled between the power terminal and a secondinternal node, a third MOS transistor coupled between the first internalnode and a third internal node; a fourth MOS transistor coupled betweenthe second internal node and a fourth internal node; a fifth MOStransistor coupled between the third internal node and a ground voltage;and a sixth MOS transistor coupled between the fourth internal node andthe ground voltage.
 20. The device of claim 19, wherein the first MOStransistor and the second MOS transistor each have a relatively thickgate insulation layer, and the third MOS transistor, fourth MOStransistor, fifth MOS transistor and sixth MOS transistor each have arelatively thin gate insulation layer,
 21. The device of claim 19,wherein the power supply voltage is an external power supply voltage forthe device or an internal power supply voltage of the device, and thesecond low voltage is one of the power supply voltage, a voltage lowerthan the power supply voltage, and a voltage between the power supplyvoltage and the first high voltage.
 22. The device of claim 19, whereinthe first MOS transistor is controlled by a voltage of the secondinternal node, and the second MOS transistor is controlled by a voltageof the first internal node.
 23. The device of claim 19, wherein gates ofthe third and fourth MOS transistors are coupled to a second low voltagethat is lower than the first high voltage.
 24. The device of claim 23,wherein the power supply voltage is an external power supply voltage forthe device or an internal power supply voltage of the device, and thesecond low voltage is one of the power supply voltage, a voltage lowerthan the power supply voltage, and a voltage between the power supplyvoltage and the first high voltage.
 25. The device of claim 19, whereinthe first MOS transistor is controlled by a first input signal and thesixth MOS transistor is controlled by an inverted version of the firstinput signal.
 26. The device of claim 25, wherein the first input signaland its inverted version are selectable to have one of a high level ofthe second low voltage and a low level of the ground voltage.
 27. Thedevice of claim 25, wherein the first input signal includes a rowaddress signal and a block selecting signal from a memory device. 28.The device of claim 27, wherein the first internal node is coupled to arow decoder and driver block of the memory device, and the row decoderand driver block selectively drives word lines of the memory device inresponse to row address signals.
 29. The device of claim 25, wherein therow decoder and driver block includes a plurality of row decoder anddriver circuits, each row decoder and driver circuit corresponding to agiven word line, and each row decoder and driver circuit furtherincluding: a seventh MOS transistor having a source coupled to the firsthigh voltage, a drain coupled to a fifth internal node, and a gateconnected to receive a second input signal; and eighth and ninth MOStransistors serially coupled between the fifth internal node and theground voltage, wherein each of the seventh and eighth MOS transistorshave a relatively thick gate insulation layer, and the ninth MOStransistor has a relatively thin gate insulation layer; and wherein theeighth MOS transistor is controlled by a voltage of the first internalnode.
 30. The device of claim 29, further comprising: an invertercoupled to the fifth internal node, wherein the inverter drives a wordline of the memory device.
 31. The device of claim 30, wherein theinverter includes PMOS and NMOS transistors, each PMOS or NMOStransistor operating at a voltage higher than the power supply voltageand having a relatively thick gate insulation layer.
 32. A circuitdevice, comprising: a first internal circuit operating at a firstvoltage that is higher than a power supply voltage of the device; asecond internal circuit operating at a second voltage that is lower thanthe first voltage; and an interface circuit restricting a voltagetransmitted from the first internal circuit to the second internalcircuit.
 33. The circuit device of claim 32, wherein the first internalcircuit includes a first MOS transistor that has a relatively thick gateinsulation layer, the second internal circuit includes a second MOStransistor that has a relatively thin gate insulation layer, and thevoltage transmitted from the first internal circuit to the secondinternal voltage reduces an electric field applied to the gateinsulation layer of the second MOS transistor.
 34. The device of claim32, wherein the interface circuit includes a third MOS transistoroperating at one of the first voltage and second voltage and having arelatively thin gate insulation layer and operating at the secondvoltage, the voltage from the first internal circuit being applied tothe second internal circuit through the third MOS transistor.
 34. Thedevice of claim 33, wherein the interface circuit includes a third MOStransistor having a relatively thin gate insulation layer, the voltagefrom the first MOS transistor being applied to the second MOS transistorthrough the third MOS transistor.
 35. The device of claim 34, whereinthe third MOS transistor prevents the first voltage higher than thepower supply voltage from being directly applied to the drain of thesecond MOS transistor, enabling the second MOS transistor to have therelatively thin gate insulation layer.
 36. The device of claim 34,wherein the third MOS transistor reduces a gate-drain voltage of thesecond MOS transistor to alleviate the electric field applied to thegate insulation layer of the second MOS transistor.